---------------------------------------------------------------------------------- 
-- Engineer: David McNamara
-- 
-- Module Name:    ucg - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: This module takes in 50Mhz and provides a clock output for a 9600buad serial driver

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;


entity ucg is
  port (clk      : in  std_logic;
        reset    : in  std_logic;
        uart_clk : out std_logic);
end ucg;

architecture Behavioral of ucg is

begin
  process(clk, reset)
    variable count_t : integer range 0 to 324;  --count to 324 50e6/(324*16)~9600
  begin
    if reset = '1' then
      uart_clk <= '0';
      count_t  := 0;

    elsif rising_edge(clk) then
      count_t := count_t+1;
      if count_t < 324 then             --count to 324 50e6/(324*16)~9600
        uart_clk <= '0';
      else
        uart_clk <= '1';
        if count_t = 324 then
          count_t := 0;
        end if;
      end if;
    end if;

  end process;
end Behavioral;

